1. Field
This disclosure relates generally to integrated circuits, and more specifically, to a method and circuit for calibrating data capture in a memory controller.
2. Related Art
Synchronous dynamic random access memory (SDRAM) utilize one or more reference clock signals provided by a memory controller to manage data transfers via one or more data strobe signals in a data processing system. The input and output data of the SDRAM are synchronized in a predetermined relationship to the data strobe signals. Double data rate (DDR) SDRAMs allow data transfers at twice the clock rate in relationship to both the rising and falling edges of the data strobe.
Conventional DDR SDRAMs use a bi-directional data strobe signal commonly referred to as a DQS signal. A data strobe receiver receives the DQS signal from either the SDRAM or a memory controller and functions to provide a reference strobe signal to properly capture data. The memory controller may include a first-in, first-out memory (FIFO) to receive data read from the SDRAM. In some memory controller designs, it may be necessary to gate the DQS signal from the SDRAM when the DQS signal is not actively driven by the SDRAM. However, determining when to disable the DQS signal gating during a read from the SDRAM may be difficult if the timing is fixed in view of process, voltage, and temperature (PVT) variations, especially for higher-speed designs.
Therefore, what is needed is a memory controller and method for calibrating the DQS signal gating that solves one or more of the above problems.